In a superscalar architecture, a computer system can increase the efficiency of the execution unit by issuing instructions out of sequence. A superscalar architecture is a processor design that allows more than one machine instruction to be executed during a clock cycle.
In some processor designs, machine instructions are further broken into one or more microinstructions. A microinstruction is the fundamental building block of instruction set design, and typically implements an elemental task.
In a traditional superscalar design, a processor includes a scheduler and multiple execution units. The scheduler receives a sequential instruction stream, determines dependencies between the instructions, and reorders the instructions based on the dependencies to increase the efficiency of execution by allowing instructions to be executed in parallel and by removing some unnecessary pipeline delays that may result from needing to wait for the results of a prior instruction before executing a subsequent instruction. These delays may be referred to as stalls.
Processor speeds typically far surpass the speeds of main memory devices. Thus, many processor clock cycles may be required to retrieve information from main memory. One approach to increase the performance is to increase the instruction window in which a superscalar processor looks ahead to 20 to 30 instructions or more. In combination with techniques such as predictive branching and speculative execution, this lookahead technique may be used to improve the performance of a superscalar processor.
The instruction window may be increased by providing an instruction pool. Instructions may then be loaded into the instruction pool so that they may be reordered and processed with branch prediction to help prevent unnecessary stalls and to try to take advantage of otherwise unused clock cycles. While this may increase the performance of the system, it also increases the complexity of the system logic, which correspondingly increases the possibilities of design and manufacturing defects.